Role

Senior Design Engineer

(Expertise in DSP/DIP/Bus Protocols is MUST and Leadership experience is a Plus.)

Eligibility

2.5 - 3 years of experience in VLSI/Digital Communications and M.E/M.Tech in VLSI Design/Digital Communications/Digital Systems.

Required Technical Skills

Strong Designing,Debugging and Analyzing experience. Excellent knowledge of HDLs  (VHDL/Verilog) with Hardware Orientation,VLSI Design, Digital Design, Basics of Electronics, Synthesis and FPGA Prototyping Knowledge. 

 Required Soft Skills

Team Player, Dedicating, Hard working, Flexible.Should be able to work independently and self-motivative.

Optional but Desired Skills 

Leading Experience, Knowledge on Verification is Plus.Working on Xilinx ISE, Teaching Experience is an added advantage. Preferably located in Hyderabad.

Responsibilities

Leading the designing team in front and closely working with tech directors to meet the designing and developement goals. Responsible for designing the projects and deliver the projects in time. Should be well versed with designing and debugging